Re: Using virtual memory and/or disk to save reduce memory footprint
On Mar 9, 3:03 pm, Pawel Dziepak <pdzie...@quarnos.org> wrote:
James Kanze wrote:
> That's simply not true, or at least it wasn't when I did my
evaluations (admittedly on an Intel 80386, quite some time ago).
And the address space of the 80386 was considerably more than
4GB; you could address 4GB per segment. (In theory, you could
have up to 64K segments, but IIRC, in practice, there were some
That's not true. According to Intel manuals it is not possible
to use linear addresses >4GB.
And? The addressing of an Intel isn't linear. Never has been.
You will pay a performance hit when you first load a segment
register, but this is a one time affaire, normally taking
place when you switch modes.
Switching modes (or at least current cr3 what also invalidates
TLB) takes place each time you access kernel (for example by
system call) while placing it in a separated address space on
Switching modes has a definite cost. Which you always pay, each
"system call". (A "system function" in source code doesn't
always have to resolve to a "system call", with mode switch,
e.g. pthread_lock on an uncontested mutex.) Switching modes is
(or at least was on early Intel 32 bits) orthogonal to which
segment registers are loaded.
I'm not too sure what you mean by "two address spaces". If
you mean two separate segments, at least in older Intel
processors, the TLB would remain valid as long as the
segment identifier remained in a segment register; there was
one per segment.
Currently the main operating systems use protected flat model
in which segments are not really used.
In other words, currently, the main operating systems are not
using the processor to its fullest, and artificially creating
restrictions for themselves and for client code.
Virtual address spaces are created using paging. Segments have
nothing to do here.
Except if the authors of the OS understand the Intel
architecture, and want to exploit it, rather than pretending
that all the world is a VAX.
(I'll admit that I find both Windows and Linux unacceptable
here. The Intel processor allows accessing far more than
4GB; limiting a single process to 4GB is an artificial
constraint, imposed by the OS. Limiting it to even less is
That's not true. Paging doesn't allow (in 32-bit mode) virtual
memory addresses >4GB. Using extensions like PAE or PSE-36 can
only increase the amount of available physical memory. These
extension also don't support segmentation, so there is no way
single process can access more than 4GB on x86 machine in
Because of an artificial limitation in the OS. That's what I
James Kanze (GABI Software) email:email@example.com
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