Re: Double-Checked Locking pattern issue

From:
"Igor Tandetnik" <itandetnik@mvps.org>
Newsgroups:
microsoft.public.vc.language
Date:
Mon, 31 Dec 2007 13:29:22 -0500
Message-ID:
<uUSlRs9SIHA.5016@TK2MSFTNGP06.phx.gbl>
"George" <George@discussions.microsoft.com> wrote in message
news:C2975792-596A-4098-BB66-D4F11C70CE3E@microsoft.com

But seems I am wrong in understanding the purpose of your sample. Is
your sample used to prove instruction re-ordering? What are the
re-ordering do you mean? I only see two threads so mis-understand it
as demonstrating thread racing conditions. :-)

---------------------
int x = 0, y = 0;

// thread 1
x = 1;
y = 2;

// thread 2
int yy = y;
int xx = x;

On many modern architectures, it is possible to end up with xx == 0
and
yy == 2.


Thread 1 first assigns to x, then to y. One would expect that, at
certain points in time, it is possible to see three different
combinations: x == 0 and y == 0 (no assignment has yet taken place), x
== 1 and y == 0 (assignment to x has occured, but not yet to y) or x ==
1 and y == 2 (both assignments have taken place).

And yet, on modern architectures it is possible for another CPU to read
the two variables at just the wront moment and observe a seemingly
impossible combination of x == 0 and y == 2 (that is, assignment to y
has occured, but not yet to x). This counterintuitive behavior of modern
hardware makes naive implementation of DCLP incorrect.
--
With best wishes,
    Igor Tandetnik

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