Re: Am I or Alexandrescu wrong about singletons?

Joshua Maurice <>
Wed, 31 Mar 2010 02:56:56 CST
On Mar 30, 8:14 pm, Herb Sutter <> wrote:

On Tue, 30 Mar 2010 16:37:59 CST, James Kanze <>

(I keep seeing mention here of instruction reordering. In the
end, instruction reordering is irrelevant. It's only one thing
that may lead to reads and writes being reordered.

Yes, but: Any reordering at any level can be treated as an instruction
reordering -- actually, as a source code reordering. That's why all
language-level MM discussions only bother to talk about source-level
reorderings, because any CPU or cache transformations end up having
the same effect as some corresponding source-level reordering.

Not quite, no. On "weaker guarantee" processors, let's take the
following example:

start pseudo code example. Forgive me for any "typos". This is off the
top of my head and I haven't really used lambda functions.
int main()
{ int a = 0;
   int b = 0;
   int c[4];
   int d[4];
   start_thread([&]() -> void { c[0] = a; d[0] = b; });
   start_thread([&]() -> void { c[1] = a; d[1] = b; });
   start_thread([&]() -> void { c[2] = a; d[2] = b; });
   start_thread([&]() -> void { c[3] = a; d[3] = b; });
   a = 1;
   b = 2;
   cout << c[0] << " " << d[0] << '\n'
        << c[1] << " " << d[1] << '\n'
        << c[2] << " " << d[2] << '\n'
        << c[3] << " " << d[3] << endl;
//end pseudo code example

On some modern processors, most (in)famously the DEC Alpha with its
awesome split cache, this program in the real world (or something very
much like it) can print:
0 0
0 2
1 0
1 2

Specifically, this is a single execution of the program. In this
single execution, the writes "a = 1; b = 2;" are seen to happen in two
different orders, the exact same "store instructions" become visible
to other cores in different orders. There is no (sane) source code
level reordering that can achieve this. I tried to emphasize this else-
thread: you cannot think about threading in terms of "possible
interleavings of instructions". It does not portably work. Absent
synchronization, on some processors, there is no global order of

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