Re: Am I or Alexandrescu wrong about singletons?

James Kanze <>
Thu, 25 Mar 2010 00:06:13 CST
On Mar 24, 7:12 pm, Michael Doubez <> wrote:

On 24 mar, 12:33, James Kanze <> wrote:


Sorry, but executing a store instruction (or a mov with a
destination in memory) does NOT guarantee that there will be
a write cycle in main memory, ever. At least not on modern
Sparc and Intel architectures. (I'm less familiar with
others, but from what I've heard, Sparc and Intel are among
the most strict in this regard.)

I am surprised. I would have expected cache lines to be
flushed after a given amount of time in order to avoid
coherency issues. 'volatile' making it worse by *forcing* a
flush per modification (although without guaranteeing ordering
with other non-volatile memory access).

Cache lines are only part of the picture, but similar concerns
apply to them. All of the coherency issues are addressed by
considering values, not store instructions. So if you modify
the same value several times before it makes it out of the
processor, some of those "writes" are lost. (This is generally
not an issue for threading, but it definitely affects things
like memory mapped I/O.) And for better or for worse, volatile
doesn't force any flushing on any of the compilers I know; all
it does is ensure that a store instruction is executed. So that
given something like:
     int volatile a;
     int volatile b;

     // ...
     a = 1;
     b = 2;
, the compiler will ensure that the store instruction to a is
executed before the store instruction to b, but the hardware
(write pipeline, typically) may reorder the modifications to
main memory, or even in some extreme cases suppress one of them.

James Kanze

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