Re: 32-bit memory accesses on dual-core dual-Xeon processors

From:

"peter koch" <peter.koch.larsen@gmail.com>

Newsgroups:

microsoft.public.vc.language

Date:

12 Jan 2007 06:43:41 -0800

Message-ID:

<1168613020.952863.197720@v45g2000cwv.googlegroups.com>

Igor Tandetnik skrev:

"peter koch" <peter.koch.larsen@gmail.com> wrote in message
news:1168252915.306014.301740@11g2000cwr.googlegroups.com

Exactly. Now if you read the MSDN documentation, threads are
mentioned, implying that memory barriers are somehow inserted into
the code. A quick examination of the assembly output confirmed my
suspicion that no such code is generated.

What compiler version have you tested with? volatile got memory barrier
semantics as of VC8. Also, memory barriers are only emitted when the
target architecture requires them. Plain old 32bit x86 features strong
cache coherence, you would need to make IA64 build to see them.
--
With best wishes,
Igor Tandetnik

Thank you for the clarification. I did compile for x86 and saw that
nothing was there! My belief was that the newer x86 architectures did
not have strong cache coherency, but apparently I am mistaken.
What happens if you run the program on the new 64-bit computers? Will
their 32-bit emulation mode (if that is what they use - I know very
little about them) have strong coherency in that mode?

Kind regards
Peter