Re: single producer, single consumer

From:

James Kanze <james.kanze@gmail.com>

Newsgroups:

comp.lang.c++

Date:

Thu, 8 Oct 2009 03:05:42 -0700 (PDT)

Message-ID:

<9577e6e7-ceb9-4f47-8616-e2ed56d072c6@l31g2000vbp.googlegroups.com>

On Oct 8, 2:31 am, goodfella <goodfella...@gmail.com> wrote:

On Oct 6, 6:23 pm, goodfella <goodfella...@gmail.com> wrote:

I have read the following Wikipedia article about cache
coherrency:

http://en.wikipedia.org/wiki/Cache_coherence

and it seems that cache coherency guarantees the following
behavior on reads and writes of memory in the same location:

A read made by processor P1 to location X that follows a write
by another processor P2 to X must return the written value
made by P2 if no other writes to X made by any processor occur
between the two accesses. This condition defines the concept
of coherent view of memory. If processors can read the same
old value after the write made by P2, we can say that the
memory is incoherent.

The article you site is rather vague: what does it mean by "the
behavior of reads and writes to the same memory location"? Most
modern processors use not only cache in the classical sense, but
also pipelines. And none of the processors I'm familiar with
(Intel and Sparc) guarantee any sort of consistency between
processors with regards to what is in the read and write
pipelines; that would defeat the whole purpose of the pipelines.
You need special instructions (fence or memory barriers) to
guaranteed synchronization.

The above statements about cache coherency are enough to show
that my code works on systems that guarantee cache coherency.

Not knowing exactly what you mean by cache coherency, I can't
say. The code you posted does not work on Intel or Sparc
architectures.

--
James Kanze