Re: Singleton_pattern and Thread Safety
On Dec 13, 11:11 pm, "Chris M. Thomasson" <cris...@charter.net> wrote:
"James Kanze" <james.ka...@gmail.com> wrote in message
news:99d6f50b-f4a2-47df-ba53-eacb2889a106@y3g2000vbm.googlegroups.com...
On Dec 11, 4:05 pm, "Chris M. Thomasson" <cris...@charter.net> wrote:
[...]
Basically, the only architecture out there which requires
a data-dependant acquire barrier after the initial atomic load
of the shared instance pointer is a DEC Alpha...
You must know something I don't: the documentation of the Sparc
architecture definitely says that it isn't guaranteed;
Here is my initial question when I was joining up with the Sun
CoolThreads Contest:
https://coolthreads.dev.java.net/servlets/ProjectForumMessageView?for...
Here is response I got form the Sun Engineering department:
https://coolthreads.dev.java.net/servlets/ProjectForumMessageView?mes...
Which concerns one particular implementation of the Sparc
architecture, IIUC.
BTW, SPARC can run in three memory coherency modes. TSO, PSO, RMO:
I know. And the extra synchronization is only necessary in RMO.
Most current Sparc processors don't use RMO, so on most current
Sparc processors, you don't need the #LoadLoad. The key words
there, however, are "most" (which may actually be all, but I've
seen nothing which guarantees it), and "current" (which very
definitely means that you may run into problems on future
Sparcs---if such things ever exist). IIUC, PSO is usual,
however.
http://en.wikipedia.org/wiki/Memory_ordering
http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2007.09...
(read all).
Heck, SPARC in RMO mode still handles data-dependant loads!
:^)
I've also heard that it fails on Itaniums,
AFAICT, `read_barrier_depends()' is a NOP on an Itanium. You
have to consult Linux source code.
Could it be another case where current processors don't actually
take advantage of all of the freedom allowed in by the processor
architecture documents?
and that it is uncertain on
80x86. (My own reading of the Intel documentation fails to turn
up a guarantee, but I've not seen everything.)
x86 is basically TSO. `read_barrier_depends()' is NOP on all Intel
architectures I have come across.
Yes. On rereading the document you posted, I think you're
right.
BTW: I wouldn't quote Linux sources as a reference. OS's have
been known to have bugs. In the end, the only reference is the
official architecture document. (Chips have also been known to
have bugs, but generally less so than the OS. And of course,
you have to base yourself on something.)
--
James Kanze