Re: Am I or Alexandrescu wrong about singletons?
On Mar 30, 12:04 pm, Andy Venikov <swojchelo...@gmail.com> wrote:
James Kanze wrote:
On Mar 28, 10:05 pm, George Neuner <gneun...@comcast.net> wrote:
All the fence does is create a checkpoint in the
instruction sequence at which relevant load or store
instructions dispatched prior to dispatch of the fence
instruction will have completed execution.
That's not true for the two architectures whose
documentation I've studied, Intel and Sparc. To quote the
Intel documentation of MFENCE:
Performs a serializing operation on all load and store
instructions that were issued prior the MFENCE
instruction. This serializing operation guarantees that
every load and store instruction that precedes in
program order the MFENCE instruction is globally visible
before any load or store instruction that follows the
MFENCE instruction is globally visible.
Note the "globally visible".
If you read the whole sentence, you have: <1> is globally
visible before <2> is globally visible. That doesn't sound to
me as saying that <1> is globally visible.
It guarantees that if <1> is not globally visible, then neither
will <2> be. I don't know what more you might want.
I don't think that the above says that instructions that
precede MFENCE are guaranteed to be visible after the MFENCE
I don't think that "instruction completes" has any real meaning
in a modern processor. Arguably, a store instruction doesn't
complete until the data is stable in main memory. But that
doesn't stop the processor from going on and doing other things.
In practice, the ordering is all that is relevant anyway.
It does guarantee, however, that the earlier instructions are
visible before ANY of the following instructions are visible.
Which is all that is required.
[ See http://www.gotw.ca/resources/clcm.htm for info about ]
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